Integrating antilog function generator

ABSTRACT

An integrating antilog function generator including an analogto-digital converter for performing two successive dual slope integration routines. During the first integration routine, a time interval related to the magnitude of an unknown signal is determined, and a voltage proportional to the antilog of the unknown signal is generated. During the second integration routine, there is generated an output signal in digital form representative of the antilog of the magnitude of the unknown signal.

United States Patent Larsson et al.

[ 5] Mar. 14, 1972 [54] INTEGRATING ANTILOG FUNCTION GENERATOR [72]Inventors: Robert W. Larsson, Holliston; Robert L.

Scott, Medfield, both of Mass.

[52] U.S. Cl. ..235/197, 235/183, 235/150.53, 324/99 D, 328/142,328/145, 340/347 NT [51] Int. Cl. ..G06I 7/24 [58] Field ofSearch..235/183, 197; 340/347 NT, 347 AD; 328/142, 145, 146; 307/227-229;324/99 D 3,316,547 4/1967 Ammann ..340/347 3,349,390 10/1967 Glassman..340/347 3,439,187 4/1969 Strauss ..235/ 197 3,440,414 4/1969 Miller..235/197 Primary Examiner-Malcolm A. Morrison Assistant Examiner-FelixD. Gruber Attorney-Clarence R. Patty, Jr. and Walter S. Zebrowski [57]ABSTRACT An integrating antilog function generator including ananalogto-digital converter for performing two successive dual slopeintegration routines. During the first integration routine, 3 timeinterval related to the magnitude of an unknown signal is determined,and a voltage proportional to the antilog of the unknown signal isgenerated. During the second integration [56] References Cited routine,there is generated an output signal in digital form UNITED STATESPATENTS representative of the antilog of the magnitude of the unknownsignal. 3,428,794 2/ 1969 Norsworthy ..235/181 3,305,856 2/1967Jenkinson ..340/347 29 Claims,2Drawing Figures SWITCH I6 24 g DISPLAY lPULSE l MEANS 22 COUN- TER 46 1 18 I2 I SWITCH 72 26 ANALOG COMPAR'SIGNAL 5 ATOR 50 54 60 SOURCE I 36 l l 164 FLIP REFERENCE INTEGRATOR lFLOP SIGNAL lo 52 SOURCE INITIAL COND. M 66 SWITCH POBETQTIAE SWITCH S UCE 84 30 I 68 GENERATOR 1 INTEGRATING ANTILOG FUNCTION GENERATORBACKGROUND OF THE INVENTION The concept of dual slope integration inrelation to analogto-digital signal conversion is known to the priorart. In the present invention we employ a dual slope integratinganalogto-digital converter in combination with an exponential functiongenerator and additional logic circuitry connected in such a manner asto provide a digital signal representation of the antilog of themagnitude of an unknown signal. Such a system of instrumentation hasparticular utility in the chemical and biomedical arts where there isoften a need to provide a visual display or an otherwise useable signal,in digital form, representative of the ionic concentration or activityof an aqueous solution. For example, the typical specific ion activitysensor is an electrode which, when immersed into a solution, generates apotential indicative of the logarithm of the specific ion activitythereof. The magnitude of this potential can be displayed with the aidof the usual analog potential metering instrument which in turn may becalibrated to read directly in units of specific ion activity by use ofa nonlinear meter scale.

When using a digital instrument, it is often desirable to determine thespecific ion concentration or activity of a solution being investigatedin which case the output thereof must be converted through the use oflog tables, slide rule, or the like. A digital metering instmment whichcould be employed with the typical pH sensor, as well as other ionsensing electrodes, to provide an output indicative of the ionicconcentration or activity of a solution directly, rather than merely thepH thereof or a millivolt reading, would have great utility in a numberof scientific investigative fields. Such as instrument eliminates thenecessity for approximate and laborious hand and machine calculationsand is a great time saver in many instances.

SUMMARY OF THE INVENTION It is therefore an object ofv the presentinvention to provide an integrating antilog function generator capableof high accuracy in which analog signals of unknown magnitude can beconverted into digital signals representing the antilog thereof, and toprovide the advantages hereinabove noted.

Briefly according to the present invention, an integrating antilogfunction generator is provided including an analog-todigital converter.The converter generates a first time period proportional to an unknownpotential applied to the input thereof. A means is included forproviding a voltage which exponentially decays from a predeterminedvalue in accordance with the equation V=V,,e""' where V is theexponentially decaying voltage, V, is the predetermined value of theprovided voltage, t is a second time period equal to a fixed time periodminus the first time period and is also generated by said converter, andRC is the time constant determining the rate of decay. The resultingvoltage is the antilog of the unknown potential.

Additional objects, features, and advantages of the present inventionwill become apparent to those skilled in the art from the followingdescription and the drawings on which, by way of example, only thepreferred embodiment of this invention is illustrated.

BRIEF DESCRIPTION OF THE DRAWINGS FIG. 1 shows a functional circuitdiagram illustrating the preferred embodiment of the integrating antilogfunction generator of the present invention.

FIG. 2 shows a timing diagram illustrative of the condition of thevarious components of the circuit of FIG. 1 during a typical operatingsequence of the integrating antilog function generator of the presentinvention.

DETAILED DESCRIPTION A complete operating sequence of the circuit ofFIG. 1 consists of two integration routines. During the firstintegration routine, two different potentials are sequentially appliedto an integrator 10. The first potential applied during the firstintegration routine has an initially unknown magnitude and is providedby an analog signal source 12, the digital antilog representation ofwhich is to be determined in accordance with the present invention. Thesecond potential having a predetermined magnitude and a polarityopposite to that of the first potential is provided by reference signalsource 14. The object of the first integration routine is to determine atime interval representative of the magnitude of the unknown potential Eprovided by source 12.

During the second integration routine which follows, there are likewisetwo separate potentials applied to integrator 10. The first potentialapplied during the second integration routine, hereinafter referred toas the antilog potential, is generated elsewhere in the circuit duringthe first integration routine as will later be explained. This potentialcorresponds to the antilog of the magnitude of the unknown potentialprovided by source 12. The second potential to be applied to integrator10 during the second integration routine is, again, the potentialprovided by reference signal source 14. The object of the secondintegration routine is to determine a time interval representative ofthe magnitude of the antilog potential which may thereafter be convertedto an equivalent digital signal for display or utilization purposes.

The circuit of FIG. 1 includes a pulse generator 16, such as afree-running multivibrator, or other equivalent well-known means forgenerating a series of pulses 17 having equal time separations. Asequential pulse counter 18 of the usual type is adapted to provide,either continuously or upon appropriate command, a digital signal atoutput 20 indicative of the number of pulses applied to input 22 bygenerator 16 since the start of the most recent counting cycle. Acounting cycle is a series of pulses sequentially registered in counter18 or the elapsed time corresponding thereto, beginning at apredetermined pulse count, proceeding through a maximum pulse count, andending just prior to reestablishing the predetermined pulse count. Asuitable display means 24 or other digital signal utilization device isresponsively connected to output 20. Counter 18 is also provided with afull scale output 26 at which is generated a pulse, hereinafter referredto as a full scale pulse, at the end of each counting cycle coincidentwith the maximum numerical pulse count being registered in counter 18.

Counter 18 may be designed so as to automatically reset itself to apredetermined starting count, such as zero or any other convenientnumber, upon completion of each counting cycle. In the alternative,counter 18 may have provisions for being reset to the predeterminedstarting count after each counting cycle is completed by externalresetting means, not shown. The automatic reset type of counter isemployed in the present example for illustrative purposes only.

The transmission of a pulse train from generator 16 to input 22 may becontinuous, as in the present example, such that counter 18 countscontinuously through a series of cycles uninterrupted by changes in thecondition of the associated external circuitry. In this manner thecombination of generator 16 and counter 18 functions as a digital clockwhich can be used to precisely control events occurring in the externalcircuitry by means of the full scale pulses generated at regularintervals at output 26.

A main timing flip-flop 28 switches from its currently occupied state tothe opposite state each time a full scale pulse is received from output26. Once having switched, flip-flop 28 remains in the new state untilthe next succeeding full scale pulse is received, at which time it willagain switch to the opposite state. Accordingly, output 30 of flip-flop28 will exhibit a high potential during every other cycle of counter 18,and a low potential during the intervening cycles. The tenns high Maintiming flip-flop 28 controls the time duration of each of two separateand distinct dual slope integration routines performed, in part, byintegrating circuit or integrator 10. The nature of these two routinesis hereinafter explained when a typical operating sequence of thecircuit of one embodiment of the present invention is described.Integrator preferably consists of operational amplifier 32, feedbackcapacitor 34 connected between the output and input of amplifier 32, andresistor 36 in series with the input to amplifier 32. As will beappreciated by those skilled in the art, the integrator or integratingcircuit produces a time varying potential at its output 38representative of the time integral of a potential applied to its input40. Any circuit which performs this function may be utilized asintegrator 10.

Voltage level comparator 42, responsively connected to integrator output38, is adapted to monitor the voltage level at output 38 of integrator10 during each of the aforementioned integration routines. This isaccomplished by the comparator 42 generating a high potential at output44 in response to the signal at output 38 passing through apredetermined threshold level in a given direction of potential change.The high-potential signal so generated at output 44 persists until theintegrator output signal passes back through the threshold level goingin the opposite direction of potential change at which time the signalat output 44 goes low. Output 44 of comparator 42 is, in turn, connectedin energizing relation to one input of counter strobe AND gate 46, andone input of reference input gate 48.

Flip-flop 50 enables the circuit to determine which of the twointegration routines to execute during a given phase of its operatingsequence. The clock input terminal 52 of flip-flop 50 is connected tooutput 30 of flip-flop 28. Output 54 of flipflop 50 will switch from themost recently occupied level, either high or low, to the opposite leveleach time the signal at output 30 of flip-flop 28 goes from high to low.However, the signal level at output 54 will not change when the signalat output 30 of flip-flop 28 goes from low to high. Thus, the frequencyof the change of state of flip-flop 50 is exactly one-half the frequencyof the change of state of flip-flop 28. Flip-flop 50 therefore acts as afrequency divider with respect to the frequency of operation of maintiming flip-flop 28. Accordingly, output 54 is low during the first andsecond cycles of counter 18 thereby permitting the first integrationroutine of the sequence to proceed. During the third and fourth cyclesof counter 18, output 54 is high thereby permitting the secondintegration routine of the sequence to proceed.

Output 54 of flip-flop 50 is connected to an input of analog signalinput gate 56, an input of antilog integrate gate 58, and an input ofantilog reset AND-gate 60. Output 54 is also connected to an input ofcounter strobe gate 46. It will become apparent that analog signalsource 12 is electrically connected to input 40 of integrator 10 onlyduring the time interval during which output 30 of flip-flop 28 andoutput 54 of flip-flop 50 are simultaneously low, these two conditionsbeing necessary to activate analog signal input gate 56. Such conditionsexist only during the first cycle of the four-cycle operating sequenceof the circuit. Similarly, it will be noted that the antilog signal isconnected through switch 62 to input 40 only during the time intervalduring which output 30 of flip-flop 28 is low and output 54 of flip-flop50 is high, these latter two conditions being necessary to activateantilog integrate gate 58. The latter conditions exist only during thethird cycle of the four-cycle sequence. Switch 62 and switches 64, 66,68, and 70 may be field effect transistors to provide fast operation;however, other types of switches may be used and one familiar with theart may readily select a suitable switch.

Counter 18 is responsive to counter strobe gate 46 which causes thedigital information contained in counter 18 to be transferred via output20 to display means 24 at the precise time that output 44 of comparator42 goes from high to low provided that, at the same time, output 54 offlip-flop 50 is high. These conditions can occur only during the fourthcycle of the operating sequence at the instant when the number incounter 18 is representativeof the magnitude of the antilog potential.Since counter strobe gate 46 remains active from the time theaforementioned conditions occur until the conclusion of the fourth cycleof the sequence, shaper 72, a conventional pulse shaping or generatingcircuit, is utilized between gate 46 and counter 18. As is well known tothose skilled in the art, such a shaper emits a pulse of short durationonly at the instant a signal provided to its input increases its levelabruptly, as from a low to a high level. The persistance of the signalat a high level at the input to shaper 72 is of no further consequencewith respect to further activity of the shaper output. It is importantthat the pulse emitted by shaper 72 in response to counter strobe gate46 going from a low to a high condition, be of no greater time durationthan that of a single pulse generated by pulse generator 16, andpreferably less. This helps to insure that the information contained inthe counter will not change during the period of its display orutilization. If the pulse emitted by shaper 72 persisted for a timeinterval which overlapped two or more pulses generated by generator 16,the information contained in counter 18 would change while display is inprogress. As a result, the infonnation displayed would be subject toinaccurate interpretation.

A potential representative of the antilog of the signal of source 12 isgenerated in RC network 74 consisting of resistor 76 and capacitor 78connected together as shown, the combination of which may have anypredetermined time constant. A potential of predetermined magnitude isinitially established across capacitor 78 by initial condition potentialsource 80 applied across capacitor 78 to ground through switch 68, theposition of which is controlled by antilog reset gate 60. The antilogpotential is generated by pennitting capacitor 78 to discharge to groundthrough resistor 76 and switch 70 over a precise time intervalcontrolled by antilog generate AND-gate 82. Antilog generate gate 82,having one input connected to output 30 of flip-flop 28 and the otherinput connected to output 84 of reference input gate 48, is activeduring a portion of the second cycle of the operating sequence duringwhich out put 30 is high and output 84 of reference input gate 48 islow. Accordingly, during this period of activity of antilog generategate 82, switch 70 is closed and capacitor 78 is dischargingexponentially from its initial condition potential. As will behereinafter described, source 80 is disconnected from network 74 duringthis period so that an exponential discharge of capacitor 78 can takeplace. At the conclusion of the second cycle, the potential acrosscapacitor 78 represents the desired antilog of the potential supplied bysource 12 and must therefore be preserved until it can be measuredduring the immediately following second integration routine. Toaccomplish this antilog generate gate 82 is deactivated to open switch70 and isolate the charge remaining on capacitor 78.

For a better understanding of the present invention, a typical operatingsequence of the circuit of FIG. 1 will now be explained with referencealso being made to the timing diagram shown in FIG. 2.

A single operating sequence of the circuit of the present example spansthe time interval of four successive counting cycles of counter 18,beginning at time 0 when analog signal source 12 is connected tointegrator 10, and ending four counter cycles later at time T when thecircuit conditions again return to the conditions at time 0 inpreparation for a new sequence. Time axis 86 of the diagram is thereforedivided into four equal time intervals T each representing one of thecycles of counter 18 occurring in a typical sequence. Assume, forillustrative purposes, that the first counting cycle of the sequence ischosen so that immediately prior to time 0 the conditions of output 30of flip-flop 28 and output 54 of flip-flop 50 are high.

At time 0 a full scale pulse 88 is generated at output 26 which switchesflip-flop 28 so that output 30 goes low, thus switching flip-flop 50 sothat output 54 thereof also goes low. These conditions activate analogsignal input gate 56 the inputs of which are connected to the outputs offlip-flops 28 and 50. Gate 56 closes switch 64 to connect analog source12 to input 40 of integrator 10. No other gates controlling theconnection of potentials to integrator are active under theaforementioned conditions. Accordingly, assuming that the unknownpotential of source 12 is of constant magnitudeand polarity, integrator10 generates at output 38 a linearly increasing potential 90proportional to the time integral of the potential at input 40.Integration of the signal potential from analog source 12 proceedsthroughout the first counting cycle until, at the start of the secondcycle at time T counter 18 emits another full scale pulse 88 at output26.

At time T the full scale counter pulse switches flip-flop 28 and itsoutput 30 goes high. It will be observed from the waveforms of FIG. 2that since output 30 goes from low to high, a corresponding change inthe condition of the input to flip-flop 50 does not alter the lowcondition of output 54. It will also be observed that the condition ofoutput 44 of comparator 42, which has been high during the first cycledue to the positive potential 90 at output 38, also remains high. Due tothe change in state of flip-flop 28, analog signal gate 56 isdeactivated thereby removing the signal from source 12 from input 40 ofintegrator 10, and the output of reference signal input gate 48 goeshigh since the outputs from comparator 42 and flip-flop 28 are connectedto gate 48, which operates switch 66. Reference source 14 is thereforeconnected to input 40. The polarity of reference source 14 beingopposite to that of analog source 12, potential 92 at output 38 ofintegrator 10 now decreases linearly with time. At time t the potentialat output 38 reaches the threshold level of comparator 42 at which timecomparator output 44 goes low. The integrator output level remains atthe threshold voltage for the remainder of the second cycle. Thoseskilled in the art will appreciate that the time interval t, between Tand t is proportional to the magnitude of the unknown potential of thesignal from source 12. Time interval t, must be determined before theantilog potential of the input signal can be generated. Thus the numbercontained in counter 18 at time t, is representative of that magnitudeand can be displayed or otherwise utilized if desired.

When output 44 of comparator 42 goes low, the output of reference gate48 goes low thus opening switch 66 and disconnecting reference source 14from integrator 10. The remaining portion of the second cycle, which isillustrated as time period t,, is utilized to generate the antilog ofthe unknown potential E of source 12.

As output 84 of reference signal gate 48 goes low at time t output 30 offlip-flop 28 still being high, the output of antilog generate gate 82goes high thereby closing switch 70 and permitting initial conditionpotential 94 previously developed across capacitor 78 to dischargethrough resistor 76 to ground. Such voltage discharging, illustrated bynumeral 96, continues at an exponential rate for a period of time t,(Tt,,) until the end of the second counting cycle at time T The secondintegration routine begins at the start of a third cycle of counter 18at which time the antilog potential generated during the preceding cycleis applied to input 40 of integrator 10 through switch 62, the positionof which is controlled by antilog integrate AND-gate 58.

At time T the voltage across the capacitor 78 corresponds to the antilogof the unknown potential of the source 12. To preserve this voltage sothat it can be determined during the second integration routine tofollow, the full scale pulse 88 occurring at time T switches flip-flop28, causing output 30 to go low, thus deactivating antilog generate gate82, opening switch 70, and isolating the charge presently existing oncapacitor 78. As a result of output 30 going from high to low, theoutput of flip-flop 50 goes high.

The conditions are now met to activate antilog integrate gate 58, closeswitch 62 and thereby apply the antilog potential across capacitor 78 tointegrator 10. The second integration routine, which provides a digitalrepresentation of the antilog potential, is now under way and willcontinue for two counter cycles, ending at time T Potential 98 at output38 of the integrator 10 increases as the time integral of potential 100across capacitor 78. Since this change is positive, output 44 ofcomparator 42 goes high and keeps counter strobe gate 46 inactive.Integration continues until counter 18 reaches full scale at theconclusion of the third cycle at time T At time T;, a full scale pulse88 is provided at output 26 switching flip-flop 28 and causing output togo high. Output 44 of comparator 42 and output 54 of flip-flop 50 remainhigh. These conditions cause the antilog integrate gate 58 to deactivatethereby opening switch 62 and stopping integration of antilog potential100 on capacitor 78. Since potential 100 has now been fully utilized attime T capacitor 78 may now be recharged to its initial conditionpotential 94 so as to be prepared to discharge once again during thenext operating sequence. To effect charging of capacitor 78, the outputof antilog reset gate 60 goes high in response to the present conditions of flip-flops 28 and 50 at time T thereby closing switch 68 toconnect source 80 directly across capacitor 78 to ground. Capacitor 78is recharged to its initial condition potential 94 virtually.instantaneously and remains in a recharged condition until time t, inthe second counter cycle of the next sequence.

At time T reference gate 48 is activated for the second time during thepresent sequence. Switch 66 closes and reference source 14 is connectedto integrator 10 once again such that potential 102 at output 38proceeds to decrease at a linear rate with respect to time. At a time tduring the fourth counter cycle, potential 102 at output 38 will passthrough the threshold level of comparator 42, depending on the magnitudeof antilog potential 100, causing comparator output 44 to go low. Attime t,, the digital quantity contained in counter 18 is representativeof the magnitude of antilog potential 100. In

order to efiect the display of that quantity, the output of counterstrobe gate 46 goes high since at time t,, the outputs of comparator 42and flip-flop 50 are low and high, respectively. The positive goingsignal from gate 46 causes shaper 72 to emit a pulse 104 in response towhich said digital quantity contained in counter 18 at time t, istransferred to display means 24.

That RC network 74 provides a voltage V that is a function of theantilog of the potential supplied by analog signal source 12, whichpotential is referred to as E, will become apparent from the followingderivation. In connection with the description of FIG. 2, it was shownthat time period t, is proportional to signal potential E which isreceived by the circuit of FIG. 1. RC network 74 is discharged from agiven voltage level V, for a time period t, which is equal to onecounting cycle (T -T,) minus the time period t,. The voltage remainingon capacitor 78 at the end of period t, is described by the equation V=V c-k where RC is the time constant of the rate of decay of V asdetermined by the resistance of resistor 76 and capacitance of capacitor78. Although said time constant is determined by RC network 74 in thepresent example, it may be determined by any exponentially varyingsource known to one familiar with the art. In order to show that voltageV is related to the antilog of input signal potential E, potential E isexpressed as follows %K +K log A 2 where A is the desired resultantvoltage which corresponds to that developed by RC network 74. Equation(2) can be rewritten therefore,

A=1O (4) Since log A =ln A log e, then from (3):

In A=(EKi)/K log e s n 1)/ a where K K log e. Thus A= (E-K )IK Referringto FIG. 2, the maximum amplitude of the integrator voltage representedby linearly increasing potential is proportional to the analog inputsignal potential E supplied by source 12. The following equationdescribing the potential represented by reference numeral 92 can bewritten.

This means that time period t, is linearly related to E with an offset Kand slope K By starting the decay of the voltage across capacitor 78 attime t which is the end of time period t and continuing to the fixedtime T2, and then opening switch capacitor 78 discharges for timeinterval t,. For the sake of simplicity. let t ,=T2.T1. Therefore,

where K =V e 'f Substituting equation (8) into equation (12)fKrQ'fffiWF? V: K (EI '3)/ 3 where RC=K K Equation (14) is the same formas equation (7) except for constant K which can be selected as desiredby adjusting circuit parameters.

By proper selection of circuit parameters, the voltage across capacitor78 can be made proportional to the antilog of the potential supplied byanalog signal source 12. Some of the circuit parameters which can bevaried are resistor 76, capacitor 78 and the potential of the source 80.

The time period between t, and T, corresponds to the additional circuitcapacity available to determine the magnitude of larger antilogpotentials than that of the present example. At time T the conclusion ofthe fourth cycle, a full scale pulse 88 is generated at output 26 whichswitches flip-flop 28 to its low output state which in turn switchesoutput 54 of flip-flop 50 to its low state. These conditions areidentical with those which previously occurred at time 0, and thecircuit is ready to begin a new sequence similar to the sequence justconcluded.

Although the present invention has been described with respect tospecific details of a certain embodiment thereof, it is not intendedthat such details be limitations on the scope of the instant inventionexcept insofar as set forth in the following claims.

We claim: 1. An integrating antilog function generator comprising ananalog-to-digital converter, means for applying an unknown potential tothe input of said analog-to-digital converter, said analog-to-digitalconverter including means for establishing a first time periodproportional to the magnitude of said unknown potential, I

means responsive to said converter for establishing a second time periodequal to a fixed time interval minus said first time period, and meansresponsive to said converter for generating a voltage whichexponentially decays from a predetermined value in accordance with theequation kne where V is the exponentially decaying voltage, V, is thepredetermined value of the provided voltage, 1 is said second timeperiod, and RC is the time constant determining the rate of decay, thevalue of V at the end of said second time period being the antilog ofsaid unknown potential.

2. The integrating antilog function generator of claim 1 furthercomprising means responsively connected to said means for establishingsaid second time period for preventing further exponential decay of saiddecaying voltage at the end of said second time period.

3. The integrating antilog function generator of claim 1 furthercomprising means cooperatively associated with said means for generatingand responsively connected to said converter for applying said decayedvoltage from said means for generating to the input of said analog todigital converter, the converter output being a digital representationof the antilog of said unknown potential. I

4. The integrating antilog function generator of claim 1 furthercomprising means for inhibiting a digital representation of said unknownpotential at the output from said analogto-digital converter.

5. The integrating antilog function generator of claim 1 wherein saidanalog-to-digital converter includes integrating means for generating anoutput signal proportional to the time integral of an input signalapplied thereto, and

comparator means responsively connected to said integrating means forproviding a first signal at the output thereof when the integratoroutput signal is above a predetermined threshold level and a secondsignal when the integrator output signal is below said predeterminedthreshold level.

6. The integrating antilog function generator of claim 5 wherein saidintegrating means comprise an operational amplifier,

a feedback capacitor connected between the output and input of saidamplifier, and

a resistor connected in series with said input of said amplifi- 7. Theintegrating antilog function generator of claim 1 wherein said means forgenerating a voltage include an RC network comprising a resistance and acapacitance.

8. The integrating antilog function generator of claim 7 furthercomprising means connected to said resistance for discharging saidcapacitance from said predetermined initial voltage V through saidresistance during said second time period.

9. The integrating antilog function generator of claim 8 wherein saidmeans for discharging include a switch connected in series with saidresistance.

10. The integrating antilog function generator of claim 7 furthercomprising means cooperatively associated with said RC network forcharging said capacitance to said predetermined initial voltage V 11.The integrating antilog function generator of claim 1 wherein saidanalog to digital converter includes a pulse generator,

a pulse counter connected to said pulse generator, and

display means connected to said pulse counter.

12. The integrating antilog function generator of claim 11 wherein saidanalog to digital converter further includes integrating means forgenerating an output signal proportional to the time integral of aninput signal applied thereto, and comparator means responsivelyconnected to said integrating means for providing a first signal levelat the output thereof when the integrator output signal is above apredetermined threshold level and a second signal level when theintegrator output signal is below said predetermined threshold level.

13. The integrating antilog function generator of claim 12 furthercomprising means responsively connected to said means for establishingsaid second time period for preventing further exponential decay of saiddecaying voltage at the end of said second time period,

means for inhibiting a digital representation of said unknown potentialat the output from said analog-to-digital converter, and

means cooperatively associated with said means for generating a voltageand responsively connected to said converter for applying said decayedvoltage from said means for generating a voltage to the input of saidintegrating means,

the converter output being the antilog of said unknown potential andbeing digitally displayed on said display means. 14. An integratingantilog function generator comprising pulses,

pulse counting means responsively connected to said pulse generatingmeans for producing a digital output signal representative of the numberof pulses applied to its input and for providing signals to establishfirst, second, third, and fourth successive equal fixed time intervals,

integrating means for generating an output signal applied thereto,

comparator means responsively connected to said integrating means forproviding a first signal at the output thereof when the integratoroutput signal is above a predetermined threshold level and a secondsignal when the integrator output signal is below said predeterminedthreshold level,

means for applying an unknown potential to the input of said integratingmeans during said first fixed time interval,

means for applying a known potential to the input of said integratingmeans at the start of said second fixed time interval for a first timeperiod proportional to the magnitude of said unknown potential,

an RC network including a resistance and a capacitance having apredetermined time constant,

means cooperatively associated with said RC network for charging saidcapacitance to a predetermined initial voltage ar means responsive tosaid comparator means for exponentially discharging said capacitancefrom said predetermined initial voltage V, through said resistance inaccordance with the equation V=V,e""", where V is the exponentiallydecaying voltage, t is a second time period equal to said second fixedtime interval minus said first time period, and RC is the time constantdetermining the rate of decay, the value of Vat the end of said secondtime period being the antilog of said unknown potential,

means cooperatively associated with said RC network and responsivelyconnected to said pulse counting means for applying said decayed voltageto the input of said integrating means at the start of said third fixedtime interval, and

means responsive to the output of said comparator for providing a signalto said pulse counting means during. said fourth fixed time interval,the corresponding output from said pulse counting means during saidfourth fixed time interval being a digital representation of the antilogof said unknown potential.

15. The integrating antilog function generator of claim 14 furthercomprising means responsive to said pulse counting means fordiscontinuing further exponential decay of said, decaying voltage at theend of said second time period.

16. The integrating antilog function generator of claim 15 furthercomprising a frequency dividing means, the input of which isresponsively connected to said pulse counting means.

17. The integrating antilog function generator of claim 16 5 whereinsaid means for providing a signal to said pulse counting means comprisea counter strobe AND gate responsively connected to said comparator andfrequency dividing means, and a pulse shaper connected between theoutput of said counter strobe gate and said pulse counting means, saidshaper being adapted to activate said pulse counting.

means to produce said digital output signal. 18. The integrating antilogfunction generator of claim 14 further comprising means for inhibiting adigital representation of said unknown potential at the output from saidpulse counting means. g 1 19. The integrating antilog function generatorof claim 14 wherein said integrating means comprise an operationalamplifier,

a feedback capacitor connected between the output and input of saidamplifier, and

a resistor connected in series with said input to said amplifi- .0--.20. The integrating antilog function generator of claim 14 10 furthercomprising a frequency dividing means, the input of which isresponsively connected to said pulse counting means.

21. The integrating antilog function generator of claim 20 wherein saidfrequency dividing means is a flip-flop.

22. The integrating antilog function generator of claim 14 wherein saidmeans for applying an unknown potential comprise a first switchconnected in series with the input to said integrating means, and

a first AND gate operatively associated with said first switch andresponsively connected to said pulse counting means.

23. The integrating antilog function generator of claim 22 wherein saidmeans for applying a known potential comprise a second switch connectedin series with the input to said integrating means, and

a second AND gate operatively associated with said second switch andresponsively connected to said pulse counting means and said comparatormeans.

24. The integrating antilog function generator of claim 14 wherein saidmeans for discharging said capacitance comprise a third switch seriesconnected to said resistance, and

a third AND gate operatively associated with said third switch andresponsively connected to said comparator means.

25. The integrating antilog function generator of claim 14 wherein saidmeans for applying said decayed voltage to said integrating meanscomprise a fourth switch series connected between the input to saidintegrating means and said capacitance, and

a fourth AND gate operatively associated with said fourth switch andresponsively connected to said pulse counting means.

26. The integrating antilog function generator of claim 20 wherein saidmeans for providing a signal to said pulse counting means comprise acounter strobe AND gate responsively connected to said comparator andfrequency dividing means, and

a pulse shaper connected between the output of said counter strobe gateand said pulse counting means, said shaper being adapted to activatesaid pulse counting means to produce said digital output signal.

27. The integrating antilog function generator of claim 26 furthercomprising means responsive to said pulse counting means fordiscontinuing further exponential decay of said decaying voltage at theend of said second time period.

28. The integrating antilog function generator of claim 27 wherein saidmeans for applying an unknown potential comprise a first switchconnected in series with the input to said integrating means, and

a first AND gate operatively associated with said first switch andresponsively connected to said pulse counting means, wherein the meansfor applying a known potential comprise a second switch connected inseries with the input to said integrating means, and

a second AND gate operatively associated with said second switch andresponsively connected to said pulse counting means and said comparatormeans, wherein said means for discharging said capacitance comprise athird switch series connected to said resistance, and a third AND gateoperatively associated with said third switch and responsively connectedto said comparator means, and wherein said means for applying saiddecayed voltage to said integrating means comprise a fourth switchseries connected between the input to said integrating means and saidcapacitance, and

A fourth AND gate operatively associated with said fourth switch andresponsively connected to said pulse counting means.

29. An integrating antilog function generator comprising ananalog-to-digital converter,

means for applying an unknown potential to the input of 4 saidanalog-to-digital converter, said analog-to-figital 12 in accordancewith the equation V=V where V is the value of said voltage at the end ofsaid second time period, V,, is the value of a predetermined constantvoltage, t is said second time period, and R and C are constants, thevalue of Vat the end of said second time period being the antilog ofsaid unknown potential.

2 3? UNITED STATES PATENT OFFICE v CERTIFICATE OF CORRECTION Patent No.3,649, 826 Dsted March 1 1972 Inventor(s) Robert W. Larsson and RobertL. Scott It is certified that error appears in theabove-identifiedlpatent and that said Letters Patent are herebycorrected as shown below:

Colurn 1, l ne 32, "as" should be an Column line 66-, equation a to readas follows:

(E w K )/K A 10 line 72, equation 7 to read as follows: I

(E K )/1 1- e r I Column 7, line 3, Insert line l-+ ,,equation 1O toread as follows: I V

V V e line 16, equation 11. to read as follows:

t /RC t /RC V V e e O line 18, equation 12 to read as follows: I

t /RC lines 22 and 23, equations 13 and I L to read as follows:

\ K. (E K1 )/RC L- V K e (13) J (E K )/K h e l 3 Signed and sealed this6th day of March 1973..

(SEAL) Attest;

EDWARD M.FLETCHER,JR. 4 ROBERT GOTTSCHALK Commissioner of PatentsAttesting Officer P UNITED STATES PATENT oFFicE 5s ctmmcmt OF eoEtiiNPatent No. 3,621 '7,826 te Mach l4 1W2 Inventor(s) Robert w. Larsson andRobert L. Scott It is certified that error appears in theabove-identifiedpatent and that said Letters Patent are hereby correctedas shown below:

Col'lr n 1, l ne 32, as should be an Colum 5, line 66 equation to readas follows:

(E K )/l A 1o li e 72, equation 7 to read as follows:

Column 7, line 3, insert line 1. equation 10 to vead as follows:

(t J/RC v V e line 16, equation 11. to read as follows:

t ,RC t /RC V=Ve. e

line l8, equation 12 to read as follows: I

lines 22 and 23, equations 13 and 1A to read as tollows:

K;(E K1 )/RC i V e 3) (E K )/K Signed and sealed this 6th day of March1973..

(SEAL) Attest:

EDWARD M.FLETCHER,JR. ROBERT QOTTSCHALK Attesting Officer Commissionerof Patents if

1. An integrating antilog function generator comprising ananalog-to-digital converter, means for applying an unknown potential tothe input of said analog-to-digital converter, said analog-to-digitalconverter including means for establishing a first time periodproportional to the magnitude of said unknown potential, meansresponsive to said converter for establishing a second time period equalto a fixed time interval minus said first time period, and meansresponsive to said converter for generating a voltage whichexponentially decays from a predetermined value in accordance with theequation V Voe t/RC, where V is the exponentially decaying voltage, Vois the predetermined value of the provided voltage, t is said secondtime period, and RC is the time constant determining the rate of decay,the value of V at the end of said second time period being the antilogof said unknown potential.
 2. The integrating antilog function generatorof claim 1 further comprising means responsively connected to said meansfor establishing said second time period for preventing furtherexponential decay of said decaying voltage at the end of said secondtime period.
 3. The integrating antilog function generator of claim 1further comprising means cooperatively associated with said means forgenerating and responsively connected to said converter for applyingsaid decayed voltage from said means for generating to the input of saidanalog to digital converter, the converter output being a digitalrepresentation of the antilog of said unknown potential.
 4. Theintegrating antilog function generator of claim 1 further comprisingmeans for inhibiting a digital representation of said unknown potentialat the output from said analog-to-digital converter.
 5. The integratingantilog function generator of claim 1 wherein said analog-to-digitalconverter includes integrating means for generating an output signalproportional to the time integral of an input signal applied thereto,and comparator means responsively connected to said integrating meansfor providing a first signal at the output thereof when the integratoroutput signal is above a predetermined threshold level and a secondsignal when the integrator output signal is below said predeterminedthreshold level.
 6. The integrating antilog function generator of claim5 wherein said integrating means comprise an operational amplifier, afeedback capacitor connected between the output and input of saidamplifier, and a resistor connected in series with said input of saidamplifier.
 7. The integrating antilog function generator of claim 1wherein said means for generating a voltage include an RC networkcomprising a resistance and a capacitance.
 8. The integrating antilogfunction generator of claim 7 further comprising means connected to saidresistance for discharging said capacitance from said predeterminedinitial voltage Vo through said resistance during said second timeperiod.
 9. The integrating antilog function generator of claim 8 whereinsaid means for discharging include a switch connected in series withsaid resistance.
 10. The integrating antilog function generator of claim7 further comprising means cooperatively associated with said RC networkfor charging said capacitance to said predetermined initial voltage Vo.11. The integrating antilog function generator of claim 1 wherein saidanalog to digital converter includes a pulse generator, a pulse counterconnected to said pulse generator, and display means connected to saidpulse counter.
 12. The integrating antilog function generator of claim11 wherein said analog to digital converter further includes integratingmeans for generating an output signal proportional to the time integralof an input signal applied thereto, and comparator means responsivelyconnected to said integrating means for providing a first signal levelat the output thereof when the integrator output signal is above apredetermined threshold level and a second signal level when theintegrator output signal is below said predetermined threshold level.13. The integrating antilog function generator of claim 12 furthercomprising means responsively connected to said means for establishingsaid second time period for preventing further exponential decay of saiddecaying voltage at the end of said second time period, means forinhibiting a digital representation of said unknown potential at theoutput from said analog-to-digital converter, and means cooperativelyassociated with said means for generating a voltage and responsivelyconnected to said converter for applying said decayed voltage from saidmeans for generating a voltage to the input of said integrating means,the converter output being the antilog of said unknown potential andbeing digitally displayed on said display means.
 14. An integratingantilog function generator comprising pulse generating means forgenerating a series of equal time pulses, pulse counting meansresponsively connected to said pulse generating means for producing adigital output signal representative of the number of pulses applied toits input and for providing signals to establish first, second, third,and fourth successive equal fixed time intervals, integrating means forgenerating an output signal applied thereto, comparator meansresponsively connected to said integrating means for providing a firstsignal at the output thereof when the integrator output signal is abovea predetermined threshold level and a second signal when the integratoroutput signal is below said predetermined threshold level, means forapplying an unknown potential to the input of said integrating meansduring said first fixed time interval, means for applying a knownpotential to the input of said integrating means at the start of saidsecond fixed time interval for a first time period proportional to themagnitude of said unknown potential, an RC network including aresistance and a capacitance having a predetermined time constant, meanscooperatively associated with said RC network for charging saidcapacitance to a predetermined initial voltage Vo, means responsive tosaid comparator means for exponentially discharging said capacitancefrom said predetermined initial voltage Vo through said resistance inaccordance with the equation V Voe t/RC, where V is the exponentiallydecaying voltage, t is a second time period equal to said second fixedtime interval minus said first time period, and RC is the time constantdetermining the rate of decay, the value of V at the end of said secondtime period being the antilog of said unknown potential, meanscooperatively associated with said RC network and responsively connectedto said pulse counting means for applying said decayed voltage to theinput of said integrating means at the start of said third fixed timeinterval, and means responsive to the output of said comparator forproviding a signal to said pulse counting means during said fourth fixedtime interval, the corresponding output from said pulse counting meansduring said fourth fixed time interval being a digital representation ofthe antilog of said unknown potential.
 15. The integrating antilogfunction generator of claim 14 further comprising means responsive tosaid pulse counting means for discontinuing further exponential decay ofsaid decaying voltage at the end of said second time period.
 16. Theintegrating antilog function generator of claim 15 further comprising afrequency dividing means, the input of which is responsively connectedto said pulse counting means.
 17. The integrating antilog functiongenerator of claim 16 wherein said means for providing a signal to saidpulse counting means comprise a counter strobe AND gate responsivelyconnected to said comparator and frequency dividing means, and a pulseshaper connected between the output of said counter strobe gate and saidpulse counting means, said shaper being adapted to activate said pulsecounting means to produce said digital output signal.
 18. Theintegrating antilog function generator of claim 14 further comprisingmeans for inhibiting a digital representation of said unknown potentialat the output from said pulse counting means.
 19. The integratingantilog function generator of claim 14 wherein said integrating meanscomprise an operational amplifier, a feedback capacitor connectedbetween the output and input of said amplifier, and a resistor connectedin series with said input to said amplifier.
 20. The integrating antilogfunction generator of claim 14 further comprising a frequency dividingmeans, the input of which is responsively connected to said pulsecounting means.
 21. The integrating antilog function generator of claim20 wherein said frequency dividing means is a flip-flop.
 22. Theintegrating antilog function generator of claim 14 wherein said meansfor applying an unknown potential comprise a first switch connected inseries with the input to said integrating means, and a first AND gateoperatively associated with said first switch and responsively connectedto said pulse counting means.
 23. The integrating antilog functiongenerator of claim 22 wherein said means for applying a known potentialcomprise a second switch connected in series with the input to saidintegrating means, and a second AND gate operatively associated withsaid second switch and responsively connected to said pulse countingmeans and said comparator means.
 24. The integrating antilog functiongenerator of claim 14 wherein said means for discharging saidcapacitance comprise a third swItch series connected to said resistance,and a third AND gate operatively associated with said third switch andresponsively connected to said comparator means.
 25. The integratingantilog function generator of claim 14 wherein said means for applyingsaid decayed voltage to said integrating means comprise a fourth switchseries connected between the input to said integrating means and saidcapacitance, and a fourth AND gate operatively associated with saidfourth switch and responsively connected to said pulse counting means.26. The integrating antilog function generator of claim 20 wherein saidmeans for providing a signal to said pulse counting means comprise acounter strobe AND gate responsively connected to said comparator andfrequency dividing means, and a pulse shaper connected between theoutput of said counter strobe gate and said pulse counting means, saidshaper being adapted to activate said pulse counting means to producesaid digital output signal.
 27. The integrating antilog functiongenerator of claim 26 further comprising means responsive to said pulsecounting means for discontinuing further exponential decay of saiddecaying voltage at the end of said second time period.
 28. Theintegrating antilog function generator of claim 27 wherein said meansfor applying an unknown potential comprise a first switch connected inseries with the input to said integrating means, and a first AND gateoperatively associated with said first switch and responsively connectedto said pulse counting means, wherein the means for applying a knownpotential comprise a second switch connected in series with the input tosaid integrating means, and a second AND gate operatively associatedwith said second switch and responsively connected to said pulsecounting means and said comparator means, wherein said means fordischarging said capacitance comprise a third switch series connected tosaid resistance, and a third AND gate operatively associated with saidthird switch and responsively connected to said comparator means, andwherein said means for applying said decayed voltage to said integratingmeans comprise a fourth switch series connected between the input tosaid integrating means and said capacitance, and a fourth AND gateoperatively associated with said fourth switch and responsivelyconnected to said pulse counting means.
 29. An integrating antilogfunction generator comprising an analog-to-digital converter, means forapplying an unknown potential to the input of said analog-to-digitalconverter, said analog-to-digital converter including means forestablishing a first time period proportional to the magnitude of saidunknown potential, means responsive to said converter for establishing asecond time period equal to a fixed time interval minus said first timeperiod, and means responsive to said converter for providing a voltagein accordance with the equation V Voe t/RC, where V is the value of saidvoltage at the end of said second time period, Vo is the value of apredetermined constant voltage, t is said second time period, and R andC are constants, the value of V at the end of said second time periodbeing the antilog of said unknown potential.